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MD1811
Initial Release
High Speed Quad MOSFET Driver
Features
6ns rise and fall time 2 A peak output source/sink current 1.2V to 5V input CMOS compatible 5V to 12V total supply voltage Smart Logic threshold Low jitter design Quad matched channels Drives two N and two P Channel MOSFETs Outputs can swing below ground Low inductance quad flat no-lead package
General Description
The Supertex MD1811 is a high speed, quad MOSFET driver designed to drive high voltage P/N-channel MOSFETs for medical ultrasound applications and other applications requiring a high output current for a capacitive load. The high-speed input stage of the MD1811 can operate from a 1.2 to 5.0 volt logic interface with an optimum operating input signal range of 1.8 to 3.3 volts. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground referenced, even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. The output stage of the MD1811 has separate power connections enabling the output signal L and H levels to be chosen independently from the supply voltages used for the majority of the circuit. As an example, the input logic levels may be 0 and 1.8 volts, the control logic may be powered by +5 and -5 volts, and the output L and H levels may be varied anywhere over the range of -5 to +5 volts. The output stage is capable of peak currents of up to 2 amps, depending on the supply voltages used and load capacitance present. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A & C output high and the B & D output low. This assists in properly pre-charging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair.
High-performance thermally-enhanced
Applications
Medical ultrasound imaging Piezoelectric transducer drivers Nondestructive evaluation PIN diode driver Clock driver/buffer High speed level translator
Typical Application Circuit
+100V +10V 0.22 F +10V 1F 0.47 F VDD VH OUTA 10nF INB OUTB Supertex TC6320 -100V 1F INC OUTC +100V 1F IND GND VSS OUTD VL 10nF 10nF
ENAB +PLS1 #1 3.3V CMOS Logic Inputs -PLS1
OE INA
To Piezoelectric Transducer #1
+PLS2 #2 -PLS2
To Piezoelectric Transducer #2
Supertex MD1811
10nF
-100V Supertex TC6320 1F
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MD1811
Ordering Information
DEVICE MD1811 JA Package Options 16-Lead 4x4x0.9 QFN MD1811K6-G 45C/W (1oz. 4-layer 3x4inch PCB) Product Marking Information 1ST Line 2
ND
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings*
VDD-VSS, Logic Supply Voltage VH, Output High Supply Voltage VL, Output Low Supply Voltage Vss, Low Side Supply Voltage Logic Input Levels Maximum Junction Temperature Storage Temperature Soldering Temperature Package Power Dissipation -0.5V to +13.5V VL-0.5V to VDD+0.5V VSS-0.5V to VH+0.5V -7V to +0.5V VSS-0.5V to VSS+7V +125C -65C to 150C 235C 2.2W
Device Number Year, Week Code, Lot Number
1811 YWLL
Line
Example: 5A88 means Lot #88 of first or second week in 2005
Pin 1
1811 YWLL
Top View
*Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
DC Electrical Characteristics (V
Sym.
VDD-VSS VSS VH VL IDDQ IHQ IDD IH VIH VIL IIH IIL VIH VIL RIN CIN
H
= VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25C)
Parameter
Logic supply voltage Low side supply voltage Output high supply voltage Output low supply voltage VDD quiescent current VH quiescent current VDD average current VH average current Input logic voltage high Input logic voltage low Input logic current high Input logic current low OE Input logic voltage high OE Input logic voltage low Input logic impedance to GND Logic input capacitance
Min.
4.5 -5.5 VSS+2 VSS
Typ.
Max.
13 0 VDD VDD-2
Units
V V V V mA A mA mA
Conditions
0.8 10 8.0 26 VOE-0.3 0 5 0.3 1.0 1.0 1.2 0 12 20 5 5 0.3 30 10
No input transitions, OE = 1 One channel on at 5.0Mhz, No load
V V A A V V K pF For logic input OE For logic inputs INA, INB, INC, and IND
Outputs (V
Sym.
RSINK RSOURCE ISINK ISOURCE
H
= VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25C)
Parameter
Output sink resistance Output source resistance Peak output sink current Peak output source current
Min.
Typ.
Max.
12.5 12.5
Units
A A
Conditions
ISINK = 50mA ISOURCE = 50mA
2.0 2.0
2
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MD1811
AC Electrical Characteristics (V
Sym.
tirf tPLH tPHL tPOE tr tf l tr - tf l l tPLH-tPHL l tdm
H
= VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25C)
Parameter
Input or OE rise & fall time Propagation delay when output is from low to high Propagation delay when output is from high to low Propagation delay OE to output Output rise time Output fall time Rise and fall time matching Propagation low to high and high to low matching Propagation delay matching
Min.
Typ.
Max.
10
Units
ns ns ns ns ns ns ns
Conditions
Logic input edge speed requirement
7 7 9 6 6 1.0 1.0 2.0
CLOAD = 1000pF, see timing diagram Input signal rise/fall time 2ns
for each channel ns ns Device to device delay match
Logic Truth Table
Logic Inputs
OE H H H H L OE H H H H L INA L L H H X INC L L H H X INB L H L H X IND L H L H X OUTA VH VH VL VL VH OUTC VH VH VL VL VH
Output
OUTB VH VL VH VL VL OUTD VH VL VH VL VL
Timing Diagram and VTH / VOE Curve
1.8V IN 0V tPLH 12V OUT 0V
10% 90 % 50% 5 0%
VTH vs VOE
VTH
VOE/2
2.0 1.5
tPHL
9 0%
1.0 0.6V 0.5
10%
0
tr
tf
0
1.0
2.0
3.0
4.0
5.0
VOE
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Simplified Block Diagram
VD D VH
MD1811
OE IN A
MD1811
OUTA
OUTB IN B
OUTC IN C
OUTD IN D
GND
VS S
VL
Detailed Block Diagram
V DD
OE
Level Shifter Level Shifter
VH
INA
OUTA
VSS VDD
VL VH
INB
Level Shifter
OUTB
VSS VDD
VL VH
INC
Level Shifter
OUTC
V SS VDD
VL VH
IND
Level Shifter
OUTD
SUB
GND
VSS
VL
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MD1811
Application Information
For proper operation of the MD1811, low inductance bypass capacitors should be used on the various supply pins. The GND pin should be connected to the logic ground. The INA, INB INC, IND, and OE pins should be connected to a logic source with a swing of GND to VLL, where VLL is 1.2 to 5.0 volts. Good trace practices should be followed corresponding to the desired operating speed. The internal circuitry of the MD1811 is capable of operating up to 100MHz, with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. Unless the load specifically requires bipolar drive, the VSS, and VL pins should have low inductance feed-through connections directly to a ground plane. If these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. The power connection VDD should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the power leads. The voltages of VH and VL decide the output signal levels. These two pins can draw fast transient currents of up to 2A, so they should be provided with an appropriate bypass capacitor located next to the chip pins. A ceramic capacitor of up to 1.0F may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. Pay particular attention to minimizing trace lengths, current loop area and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. This will of course reduce the output voltage slew rate at the terminals of a capacitive load. Pay particular attention that parasitic couplings are minimized from the output to the input signal terminals. The parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.2V even small coupled voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry.
Pin Description
VDD VSS VH VL GND High side analog circuit, level shifter and gate drive supply voltage. Low side analog circuit, level shifter and gate drive supply voltage. VSS must be connected to the most negative potential of voltage supplies and powered-up first. Supply voltage for P-channel output stage Supply voltage for N-channel output stage Logic input ground reference Output-Enable logic input. When OE is high, (VOE+VGND)/2 sets the logic threshold level for inputs, When OE is low, OUTA and OUTC are at VH, OUTB and OUTD are at VL, regardless of the inputs INA, INB, INC or IND. Keep OE low until IC powered up Logic input. Controls output when OE is high. Input logic high will cause the output to swing to VL. Input logic low will cause the output to swing to VH. Keep all logic inputs low until IC powered up. Output driver. Swings from VH to VL. Intended to drive the gate of an external P-channel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTA will swing to VH turning off the external P-channel MOSFET. Output driver. Swings from VH to VL. Intended to drive the gate of an external N-channel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTB will swing to VL turning off the external N-channel MOSFET. Output driver. Swings from VH to VL. Intended to drive the gate of an external P-channel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTC will swing to VH turning off the external P-channel MOSFET. Output driver. Swings from VH to VL. Intended to drive the gate of an external N-channel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTD will swing to VL turning off the external N-channel MOSFET. The IC substrate is internally connected to the thermal pad. Thermal Pad and VSS must be connected externally.
OE
INA, INB, INC, IND
OUTA
OUTB
OUTC
OUTD
Substrate
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MD1811
Pin Configuration
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Note
Function INB VL GND VL INC IND VSS OUTD OUTC VH VH OUTB OUTA VDD INA OE
Thermal Pad, and Pin #7 (VSS), must be connected externally
2.64 16 13
1
12
QFN-16 4x4x0.9
4 9
2.64
5 0.325 0.65
8 0.28
(Top View, mm)
Doc.# DSFP - MD1811
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